Résumé
Modern processors use performance-boosting techniques like speculative execution and multi-level caching. Unfortunately, these same optimizations can unintentionally create security vulnerabilities known as microarchitectural sidechannels. The core novelty of this work is a precise, simulationdriven method to pinpoint exactly how individual cryptographic instructions leak information. We present a systematic analysis of common AES instructions (such as AESENC, AESDEC, and AESKEYGENASSIST), measuring their vulnerability to Flush+Reload side-channel attacks. By using cycle-accurate gem5 simulations, we were able to isolate and analyze each instruction's unique leakage pattern. The AESENC instruction causes significant timing variations and L1 data cache misses (76%) due to its S-box table lookups. The AESKEYGENASSIST instruction shows the highest latency, stemming from its iterative key expansion process. Nearby branch instructions (like JNE) worsen the leakage by introducing frequent mispredictions. A key finding is that our gem5 simulation environment reliably mirrors real hardware behaviour, achieving 89% key recovery accuracy compared to 96% on a physical Intel CPU. This validation confirms that simulations can effectively capture these subtle vulnerabilities without real-world noise. We also show that smaller caches amplify leakage by concentrating memory accesses, while larger caches only reduce, not eliminate, the risk. Ultimately, our findings provide actionable insights for developers to harden cryptographic code and for designers creating future detection tools. This work demonstrates the critical role of architectural simulation in identifying and understanding security vulnerabilities before chips are even built.