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Modeling Gate Oxide Short Defects in CMOS Minimum Transistors
Acte de colloque   Open Access

Modeling Gate Oxide Short Defects in CMOS Minimum Transistors

Michel Renovell, Jean-Marc J.-M. Galliere, Florence Azaïs et Yves Bertrand
7th IEEE European Test Workshop, pp.15-20
ETW: European Test Workshop (Corfu, Greece, 2002)
2002

Résumé

In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

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