Résumé
Modern integrated circuits such as System-On-Chip (SoC) require substantial memory capacity to operate. To ensure the reliability of these computing systems, high memory quality must be maintained, making continuous improvements in memory testing essential. To prevent any limitation from the widely used functional memory test strategy, regarding the context of ever-increasing complexity in memories, structural testing has been proposed as an effective method for improving memory testing. Structural testing methodologies requiring a digital memory modeling has enabled the use of powerful tools from the digital domain, such as Fault Simulators (FS) and Automatic Test Pattern Generators (ATPG) in memory testing. Leveraging digital memory modeling, this work proposes HCM (Hardware Context Monitoring), a modular methodology for modeling complex memory faults (i.e. dynamic and multi-cell dynamic) within a digital test environment. HCM enables the evaluation of test algorithms in terms of their ability to detect complex faults, and it supports fault-oriented, optimized, and automated test pattern generation. Experimental results using dRDF case study while considering stress effects in the memory array demonstrate the effectiveness of HCM in assessing the fault coverage capabilities of various March algorithms.