Low cost partial scan design: a high level synthesis approach

M.L. Flottes; R. Pires; B. Rouzeyre; L. Volpe; IEEE COMP SOC

doi:10.1109/VTEST.1998.670887

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Low cost partial scan design: a high level synthesis approach

M.L. Flottes, R. Pires, B. Rouzeyre, L. Volpe et IEEE COMP SOC

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231), pp.332-340

1998

DOI: https://doi.org/10.1109/VTEST.1998.670887

Résumé

Automatic test pattern generation

Controllability

Costs

Delay

High level synthesis

Observability

Open loop systems

Pins

Robots

Testing

In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.

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Détails

Titre: Low cost partial scan design: a high level synthesis approach
Créateurs - sans rôle: M.L. Flottes - Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
R. Pires
B. Rouzeyre
L. Volpe
IEEE COMP SOC
Détails de publication: Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231), pp.332-340
Éditeur: IEEE
Nombre de pages: 9
Identifiants: 99139260909311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Langue: English
Type de ressource: Conference proceeding