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Low Voltage Testing of Gate Oxide Short in CMOS Technology
Acte de colloque

Low Voltage Testing of Gate Oxide Short in CMOS Technology

Michel Renovell, Jean-Marc J.-M. Galliere, Florence Azaïs et Yves Bertrand
5th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp.168-174
DDECS: Design and Diagnostics of Electronic Circuits and Systems (Brno, Czech Republic, 2002)
2002

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