Résumé
Side-channel attacks (SCAs) exploit physical leakage vectors, including cache states, timing variations, and power consumption in hardware microarchitectures to compromise computational security. This paper introduces an end-to-end, simulation-driven framework that integrates gem5's cycle-accurate architectural models with unsupervised machine learning to automate SCA detection. We simulate Spectre (V1/V2), Prime+Probe, and Flush+Reload attack pattern workloads to generate fine-grained execution traces encompassing BTB access sequences, memory latency distributions, and pipeline stall events. Temporal feature engineering extracts discriminative signatures through branch predictor entropy calculations and miss sequence autocorrelation, while dimensionality reduction via t-SNE optimizes the feature space. These preprocessed traces train an ensemble of Isolation Forest, Variational Autoencoders, and HDBSCAN models to identify attack patterns without predefined templates. Experimental validation demonstrates 0.92 precision and 0.88 recall for cache-based SCAs (Prime+Probe variants), representing a 92% F1-score improvement over SVM baselines. SHAP-based feature attribution reveals BTB-miss run-lengths and memory controller contention queues as critical attack patterns. This pipeline automatically categorize interpretable attack patterns if they are risky for the system, enabling proactive identification of safe and unsafe instructions for secure hardware through gem5's reconfigurable memory hierarchy and cache partitioning mechanisms.