Résumé
Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).