Résumé
This paper presents a diagnosis methodology able to improve the diagnosis resolution by considering only the logic information provided by the tester. The main advantage of the outlined methodology is the capability to deal with several fault models at a time, both static and dynamic, setting up a unified framework for logic diagnosis able to manage also transistor level faults. Experiments on ITC'99 benchmark circuits show the efficiency of the proposed method both in terms of diagnosis resolution and required CPU time.