Résumé
This paper presents a detailed analysis of the impact of process variations on the detection of resistive short defects in 28nm Bulk and FDSOI (Fully Depleted Silicon- OnInsulator) technologies. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). A comparative study is presented for both Regular-VT devices (FDSOI-RVT and BulkLR) and Low-VT devices (FDSOI-LVT and Bulk-LL). The study is performed under nominal and low power supply operating conditions, and the possibility of using the Body Biasing option offered by the FDSOI technology is also considered. Based on Monte-Carlo simulations, defect detectability ranges are quantified for each implementation and the impact of process variations on the achieved detectability ranges is commented.