Résumé
This paper presents an attempt towards design quality improvement by incorporation of testability features during datapath high-level synthesis. This method is based on the use of hardware sharing possibilities to improve the testability of the circuit without a time consuming re-synthesis process. This is achieved by incorporating test constraints during register allocation and interconnect network generation. The main features of this method are: a test analysis at the behavioral level rather than at a structural one; the non limitation on the behavioral descriptions (loops, control constructs are supported); and the optimized test area overhead and CPU time compared to standard approach. The method was applied to several benchmarks resulting in easily testable designs for almost the same area costs as the original (without testability) designs.< >