Résumé
The openness and customizability of RISC-V processors have made them promising candidates for high-reliability applications, including radiation-harsh environments. This work presents the implementation of a RISC-V processor that integrates error detection and monitoring into redundant structures of the processor. Our key contribution is a fault-aware RISC-V SoC that enhances real-time fault analysis, system recovery, and radiation testing through improved fault model characterization. The presentation will show results from two irradiation facilities, with neutron and mixed-field irradiation spectra. This implementation has demonstrated to be effective, and provides critical insights into fault mechanisms and enable a more robust SoC design.