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Full Analyttical Model for delay Performance Estimation in Submicron CMOS
Acte de colloque

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Philippe Maurine, Nadine Azemard et Daniel Auvergne
8th Mixed Design of Integrated Circuits and Systems, pp.355-359
MIXDES: Mixed Design of Integrated Circuits and Systems (Zakopane, Poland, 21/06/2001–23/06/2001)
2001

Résumé

In this paper we develop a simple and accurate analytical model of the supply current, the output transition time and the delay of inverters designed in submicron technologies. This model considers velocity saturation, load and input ramp effect and also input to output coupling phenomena. Validations are given, on a 0.18μm process, by comparing values of simulated (Hspice) and calculated delay for different configurations of inverters.

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