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Electrical Modeling of LSCRs in Deep Submicron CMOS Technologies for Circuit-Level Simulation of ESD
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Electrical Modeling of LSCRs in Deep Submicron CMOS Technologies for Circuit-Level Simulation of ESD

Benjamin Caillard, Florence Azaïs, Pascal Nouet, Stéphanie Dournelle et Pascal Salomé
BCTM 2003 - Bipolar/BiCMOS Circuits and Technology Meeting, pp.97-100
BCTM 2003 - Bipolar/BiCMOS Circuits and Technology Meeting (Toulouse, France, 28/09/2003–30/09/2003)
2003

Résumé

This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PiN diode model for the post-triggering behaviour. As an illustration, the model has been validated against silicon in both 0.18/spl mu/m and 0.13/spl mu/m technologies.

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