Résumé
PVT information is mandatory to control specific knobs to compen-sate the variability effects. In this paper, we propose a new on-chip monitoring system and its associated integration flow, allowing timing failure anticipation in real-time, observing the timing slack of a pre-defined set of observable flip-flops. This system is made of specific structures located nearby the flip-flops, coupled with a detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area, fine-grain system. The integration flow re-sults exhibit the weak impact of the insertion of this monitoring system toward the large benefits of tuning the circuit at its optimum working point.