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Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology
Acte de colloque

Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology

Régis Roubadia, Sami Ajram et Guy Cathébras
ISCAS'07: IEEE International Symposium on Circuits and Systems, pp.2490-2493
ISCAS'07: IEEE International Symposium on Circuits and Systems (New Orleans, LA, USA, 27/05/2007–30/05/2007)
05/2007
DOI: https://doi.org/10.1109/ISCAS.2007.378744

Résumé

CMOS Integrated Circuits Phase Locked Loops Voltage-Controlled Oscillators Multiphase Direct Realignment Multiphase Realigned PLL Phase Locked Loop Standard CMOS Process Submicronic CMOS Technology Voltage Controlled Oscillator
This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.

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