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Design for sequential testability: an internal state reseeding approach for 100 % fault coverage
Acte de colloque

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

M.L. Flottes, C. Landrault, A. Petitqueux et IEEE COMPUTER SOCIETY
Proceedings of the Ninth Asian Test Symposium, pp.404-409
2000
DOI: https://doi.org/10.1109/ATS.2000.893657

Résumé

Automatic test pattern generation Automatic testing Circuit faults Circuit testing Controllability Costs Flip-flops Observability Sequential analysis Test pattern generators
This paper proposes a method to select observation points and flip-flops for partial reset. The method does not target minimum DFT insertion but a maximum improvement on testability. The proposed non-scan approach allows a at-speed testing. Experimental results show that the method achieves 100% fault coverage and 100% fault efficiency for benchmark circuits while requiring less ATPG effort (CPU time) with no scan necessity.

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