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Design for Test Observability of an AMBA-AXI Network Interface for Reliable MPSoCs

Design for Test Observability of an AMBA-AXI Network Interface for Reliable MPSoCs

Thiago H Rausch, Wesley Grignani, Douglas A Santos, Luigi Dilillo Douglas R Melo
39th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2026) (Rome, Italy, 30/09/2026)
Network Interfaces AMBA-AXI Networks-on-Chip Fault Tolerance
Reliable Multiprocessor Systems-on-Chip (MPSoCs) require Fault-Tolerant (FT) communication to maintain correct operation in the presence of Single-Event Upsets (SEUs). For testing and validation, however, it is important to observe how hardening mechanisms behave and how fault effects are reported during execution. This work presents a new design for enhanced observability during the test of a hardened AMBA-AXI Network Interface (NI) and its supporting traffic logic within a reliable architecture. The proposed design combines a hardened communication path with an observation component and UART reporting to monitor execution progress and fault indications during test campaigns. Control-intensive structures are hardened with Triple Modular Redundancy (TMR), while memory elements are hardened with Hamming Error Correcting Codes (ECC). Synthesis, performance, and fault injection results demonstrate that, with hardware correction enabled, the hardened traffic logic remains free of failures under the evaluated injections, with residual events confined to the reporting architecture. Overall, the results show that the proposed design strengthens the NI communication path while providing the observability needed to interpret the effectiveness of the deployed hardening techniques, and it will enable the interpretation of experiments under radiation exposure in facilities.

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