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Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology
Acte de colloque   Open Access

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin M. Wilson, Philippe Roche, …
Sixteenth International Symposium on Quality Electronic Design, pp.366-370
ISQED 2015 - 16th International Symposium on Quality Electronic Design (Santa Clara, United States, 02/04/2015–04/04/2015)
03/2015
DOI: https://doi.org/10.1109/ISQED.2015.7085453

Résumé

SRAM chips Energy efficient Cache ULV RISC FDSOI wafer-level tests ultralow voltage storage capacity 8 Kbit storage capacity 32 bit size 28 nm low energy operation fully depleted silicon on insulator technology SRAM cache SPARC V8 microprocessor FDSOI technology Standards Registers Microprocessors Transistors CMOS integrated circuits Low voltage silicon-on-insulator microprocessor chips cache storage

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