Résumé
Reliability in safety-critical systems is essential for operation in environments prone to ionizing radiation. This work presents the design and reliability analysis of a hardened, 5-stage pipelined RISC-V processor integrated with a configurable and fault-tolerant instruction memory cache. To balance performance and dependability, hardening strategies, including Triple Modular Redundancy (TMR) and Error-Correcting Codes (ECC), are selectively applied to both the pipeline datapath and the cache structures, complemented by built-in observability mechanisms to track real-time error propagation. System-on-Chip (SoC) simulation results demonstrate a peak performance speedup of 3.38× with the integrated cache configurations. Physical synthesis on a SmartFusion2 M2S025 FPGA highlights the hardware tradeoffs, showing a 41% LUTs and 43% DFFs overhead for the hardened core with cache while maintaining a compact footprint. Finally, comprehensive fault-injection campaigns under simulated neutron flux reveal that while the largest baseline cache increases failure rates by 3.4×, the proposed hardening architecture achieves an average 97% reduction in error propagation, restoring the system's failure cross-section to levels comparable to that of the hardened core without cache.