Résumé
This paper presents a dc and low frequency noise characterization performed on multi gate N-MOSFET in a bulk technology by integrating polysilicon-filled trenches. This architecture provides a standard MOSFET controlled by the surface gate and multiple lateral sub-channels controlled by the lateral gate. A simple compact model predicting the current-voltage lateral transistor characteristics is proposed. Surface and lateral gate oxide interfaces are characterized. The slow oxide trap densities of the two interfaces have been extracted. The values obtained for the surface gate oxide are between N t (E Fn) =1 10 16 cm-3 eV-1 and N t (E Fn) =1 10 17 cm-3 eV-1. They are comparable to values for nitrided oxides on Si bulk. For the lateral oxide, we obtain trap densities between 1 10 15 and 1 10 17 cm-3 eV-1. According to these low values, these devices can be considered as a good candidate for analog applications.