Résumé
Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect tiers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. These are latent defects that affect circuit performance and reliability in stacked ICs and can be modeled as small-delay defects (SDDs). Due to combinations of switching activity, supply noise and crosstalk, TSV delays can experience speed-up or slowdown that could let SDDs go undetected by conventional test methods. In this work, we present a metric based on probabilistic delay analysis to detect SDDs induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accurancy of the proposed metric.