Built-In Self-Test for Manufacturing TSV Defects before bonding

Giorgio Di Natale; Marie-Lise Flottes; Bruno Rouzeyre; Hakim Zimouche

doi:10.1109/VTS.2014.6818771

Retour

Acte de colloque

Built-In Self-Test for Manufacturing TSV Defects before bonding

Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre et Hakim Zimouche

32nd VLSI Test Symposium

VTS: VLSI Test Symposium (Napa, CA, United States, 13/04/2014–17/04/2014)

04/2014

DOI: https://doi.org/10.1109/VTS.2014.6818771

Résumé

TSV

Pin-hole

PVT

BIST

3D Pre-Bond Testing

Void

In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is desi gned and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.

Fichiers et liens (1)

url

Find in HALAfficher

Indicateurs

1 Consultations de la notice

See more details

Détails

Titre: Built-In Self-Test for Manufacturing TSV Defects before bonding
Créateurs - sans rôle: Giorgio Di Natale - Centre National de la Recherche Scientifique
Marie-Lise Flottes - Université de Montpellier
Bruno Rouzeyre - Université de Montpellier
Hakim Zimouche - Centre National de la Recherche Scientifique
Détails de publication: 32nd VLSI Test Symposium
Colloque: VTS: VLSI Test Symposium (Napa, CA, United States, 13/04/2014–17/04/2014)
Identifiants: 9942381709311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00989682