Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials

Arnaud Tisserand

doi:10.1109/ACSSC.2006.355128

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Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials

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Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials

Arnaud Tisserand

40th Asilomar Conference on Signals, Systems and Computers, pp.2053-2057

40th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA (USA), 10/2006–10/2006)

10/2006

DOI: https://doi.org/10.1109/ACSSC.2006.355128

Résumé

Computer Arithmetic

Polynomial Evaluation

Low-Power Circuit

This paper presents a method for the automatic generation of high-performance and low-power arithmetic operators based on polynomial approximations. It deals with the bit-level representation of the polynomial coefficients, the intermediate computations width, the approximation and the rounding errors. The generated operators are small, fast and numerically validated at design time. Some examples have been implemented on FPGAs.

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Détails

Titre: Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials
Créateurs - sans rôle: Arnaud Tisserand - Université de Montpellier
Détails de publication: 40th Asilomar Conference on Signals, Systems and Computers, pp.2053-2057
Colloque: 40th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA (USA), 10/2006–10/2006)
Identifiants: 9942753409311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00125519