Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application

Acte de colloque

J. Liang, J. Lee, S. Berrada, V. Georgiev, A. Asenov, N. Azemard-Crestani, A. Todri-Sanial et IEEE

IEEE Nanotechnology Materials and Devices Conference, pp.66-67

IEEE Nanotechnology Materials and Devices Conference

01/01/2017

Résumé

Engineering

Engineering, Electrical & Electronic

Materials Science

Materials Science, Multidisciplinary

Nanoscience & Nanotechnology

Science & Technology

Science & Technology - Other Topics

Technology

1 Consultations de la notice

Titre: Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application
Créateurs - sans rôle: J. Liang - Univ Montpellier, CNRS LIRMM, Montpellier, France
J. Lee - Univ Glasgow, Sch Engn, Glasgow, Lanark, Scotland
S. Berrada - Univ Glasgow, Sch Engn, Glasgow, Lanark, Scotland
V. Georgiev - Univ Glasgow, Sch Engn, Glasgow, Lanark, Scotland
A. Asenov - University of Glasgow
N. Azemard-Crestani - Univ Montpellier, CNRS LIRMM, Montpellier, France
A. Todri-Sanial - Univ Montpellier, CNRS LIRMM, Montpellier, France
IEEE
Détails de publication: IEEE Nanotechnology Materials and Devices Conference, pp.66-67
Publications en série: IEEE Nanotechnology Materials and Devices Conference
Éditeur: IEEE
Nombre de pages: 2
Note de subvention: 688612 / European Union's Horizon 2020 research and innovation program H2020 CONNECT European project
Identifiants: 99136185809311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Langue: English
Type de ressource: Conference proceeding