Résumé
Conventionally, the access failures in SRAMs are treated at core cell level by means of differential bit line voltage analysis. In this work it is shown that under the assumption of random process variability, the conventional approach no longer suffices. It still holds that the differential bit line voltage is degraded by the variability in core cell transistors, but the way this voltage difference is interpreted by the sense amplifier to complete the read operation is influenced by random variability affecting its transistors. Case studies show how variability affecting the sense amplifier can degrade or improve its ability to read the data stored by the core cell, which is itself affected by variability. Using principal component analysis and the SB-SI method, we performed a parametric analysis of the sense amplifier/core cell system and we evaluated the joint probability of access failure. A three times increase in the failure probability has been observed when compared to cell's failure probability. Also, the minimum variability value for which a failure is observed is ~2.5X smaller when joint variability is assumed compared to the case when only the core cell is affected by variability.