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An intra-cell defect grading tool
Acte de colloque   Open Access

An intra-cell defect grading tool

Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi et Paolo Bernardi
17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.298-301
DDECS: Design and Diagnostics of Electronic Circuits and Systems (Warsaw, Poland, 23/04/2014–25/04/2014)
2014
DOI: https://doi.org/10.1109/DDECS.2014.6868814

Résumé

Test Intra-cell defect Fault simulation Diagnosis Dictionaries Logic gates Databases continuous scaling intra-cell defect grading tool Circuit faults Automatic test pattern generation Transistor size intra-cell diagnosis resolution Intra-cell defects scaling circuits applied test set integrated circuit testing flip-flops Integrated circuit modeling Libraries
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

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