Résumé
To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate timing violations to prevent system failures in real-time. Performances simulated in a 45 nm technology demonstrate a scalable, low power and low area cell which can be easily inserted in a standard CAD flow.