An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian; Bernd Becker

doi:10.1109/VTS.2009.57

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An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

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An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian et Bernd Becker

VTS'09: 27th VLSI Test Symposium, pp.21-26

VTS'09: 27th VLSI Test Symposium (Santa Cruz, Californie, United States, 03/05/2009–07/05/2009)

05/2009

DOI: https://doi.org/10.1109/VTS.2009.57

Résumé

VLSI

Test

Defect model

fault simulation

Resistive Short

Delay Testing

In this paper a new electrical model is proposed to be used in fault size based fault simulation of crosstalk aggravated resistive short defects. The electrical behavior of the defect is first described and analyzed in details. Then an electrical model is proposed allowing to efficiently compute the critical resistance determining the range of detectable short resistance. The model is validated by comparison with SPICE simulations.

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Titre: An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
Créateurs - sans rôle: Nicolas Houarche - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Mariane Comte - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Michel Renovell - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Alejandro Czutro - University of Freiburg
Piet Engelke - University of Freiburg
Ilia Polian - University of Freiburg
Bernd Becker - University of Freiburg
Détails de publication: VTS'09: 27th VLSI Test Symposium, pp.21-26
Colloque: VTS'09: 27th VLSI Test Symposium (Santa Cruz, Californie, United States, 03/05/2009–07/05/2009)
Identifiants: 9938402709311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00374941