Alleviating DFT cost using testability driven HLS

M L Flottes; R Pires; B Rouzeyre; IEEE COMP SOC

doi:10.1109/ATS.1998.741582

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Alleviating DFT cost using testability driven HLS

M L Flottes, R Pires, B Rouzeyre et IEEE COMP SOC

Asian Test Symposium Proceedings, pp.46-51

01/01/1998

DOI: https://doi.org/10.1109/ATS.1998.741582

Résumé

Computer Science

Computer Science, Hardware & Architecture

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

This paper presents a method to carry our the register allocation phase of High Level Synthesis with testability considerations. Testability problems al-e identified and eliminated during this step turning testability/area tradeoff to account. If allows to decrease the cost related to the application of low-level DFT techniques.

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Détails

Titre: Alleviating DFT cost using testability driven HLS
Créateurs - sans rôle: M L Flottes
R Pires
B Rouzeyre
IEEE COMP SOC
Détails de publication: Asian Test Symposium Proceedings, pp.46-51
Éditeur: IEEE
Nombre de pages: 6
Identifiants: 99139266209311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Langue: English
Type de ressource: Conference proceeding