Résumé
In this paper, we will present a near-ML (Maximum Likelihood) MIMO (Multiple Input Multiple Output) detector explicitely optimized for parallel programmable baseband architectures, such as DSPs (Digital Signal Processors) with VLIW (Very Long Instruction Word), SIMD (Single Instruction Multiple Data) or vector processing features. First, we propose the SSFE (Selective Spanning with Fast Enumeration) algorithm as an architecture friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. This enables efficient parallelization on programmable architectures. More importantly, in order to exploit the abundant flexibility enabled by programmable architectures, we propose an efficient online algorithm to adaptively adjust the search range of the SSFE according to the numerical properties of MIMO channel matrixes. Such adaptiveness brings significant throughput improvements at negligible performance degradations. Specifically, on VLIW DSP TI TMS320C6416, such a dynamic adaptation brings 2.62x to 28.6x improvements (comparing to the static SSFE) for 1/2 Turbo-coded 4 x 4 64QAM transmissions over 3GPP suburban macro channels, delivering 80 - 103 Mbps average throughput.