Résumé
The massive integration of several functionalities leads to increased test times/test data volume. Additionally, test content for more advanced fault models increase the tester memory requirements. On the positive side, the presence of many cores in a system provides the opportunity of core testing each other. In this paper we evaluate the opportunity to use AES crypto- processors as test pattern generators. Several experiences are conducted on LFSRs and AES cores in order to compare their ability to generate pseudo-random test sequences.