Résumé
Testing memory circuits is crucial to ensure the quality of a System on Chip (SoC) as technology nodes shrink, making circuits more prone to defects and reliability issues at nanometer scales. This paper presents an efficient testing flow based on an adaptation of the Cell-Aware (CA) test concept for the testing of memory address decoders. With the use of an Automatic Test Pattern Generator (ATPG), two different decoder architectures are tested for stuck and transition faults, addressing both intra and inter-cell defects. In this work, we show that this methodology results in a 100% intra and intercell defect coverage for both Transition Faults (TFs) and Stuck-At Faults (SAFs). To compare our results with existing solutions, the MATS++ algorithm has been used. A 51% improvement in TFs and 8% improvement in SAFs test coverages have been obtained through our Cell-Aware methodology.