A Simple and Effective Compression Scheme for Test Pins Reduction

Marie-Lise Flottes; Régis Poirier; Bruno Rouzeyre

doi:10.1109/HLDVT.2002.1224447

Retour

Acte de colloque

A Simple and Effective Compression Scheme for Test Pins Reduction

Marie-Lise Flottes, Régis Poirier et Bruno Rouzeyre

HLDVT 2002 - 7th IEEE International High Level Design Validation and Test Workshop, pp.165-168

HLDVT 2002 - 7th IEEE International High Level Design Validation and Test Workshop (Cannes, France, 27/10/2002–29/10/2002)

2002

DOI: https://doi.org/10.1109/HLDVT.2002.1224447

Résumé

We present a simple and effective method for test pin reduction. It must be noticed first that this method is particularly well adapted to the test of SoC since it only deals with test data and does not require any knowledge of the embedded cores. Secondly, it does not induce any delay penalty neither in the circuit itself nor during decompression.

Fichiers et liens (1)

url

Find in HALAfficher

Indicateurs

1 Consultations de la notice

Détails

Titre: A Simple and Effective Compression Scheme for Test Pins Reduction
Créateurs - sans rôle: Marie-Lise Flottes - Centre National de la Recherche Scientifique
Régis Poirier - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Bruno Rouzeyre - Centre National de la Recherche Scientifique
Détails de publication: HLDVT 2002 - 7th IEEE International High Level Design Validation and Test Workshop, pp.165-168
Colloque: HLDVT 2002 - 7th IEEE International High Level Design Validation and Test Workshop (Cannes, France, 27/10/2002–29/10/2002)
Identifiants: 99152401809311
Unité académique: Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM
Langue: English
Type de ressource: Conference proceeding
Champs locaux: lirmm-00269326