Résumé
In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can self-recover from all possible single-node upsets (SNUs) and a part of double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of parallel access transistors. Simulation results demonstrate that the proposed SCCS18T cell can approximately save 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with the state-of-the-art hardened SRAM cells.