Résumé
This article describes the design of a Programmable Logic Block (PLB) of a multi-style asynchronous FPGA. One advantage to embed asynchronous computations in FPGA is to thwart side-channel attacks on cryptographic blocks. As the main attack works by studying the power consumption we aim at making this measurement as little informative as possible. Thus the proposed PLB can handle various styles of asynchronous logic in different communication protocols (2-phase or 4-phase protocols) and data representation (1-out-of-2 or 1-out-of-3). The design is incrementally constructed startingfrom the mathematical requirements of the various functions and styles to be implemented. Eventually a versatile design is reached, supporting concomitantly any mixture of 1-out-of-2 or 1-out-of-3 representation of data under a 4-phase protocol and one 1-out-of-2.