Résumé
This paper presents a virtual library design flow for automatic layout synthesis tools. The motivation to develop such design flow is to enable the use of static CMOS complex gates (SCCGs), to optimize area and delay at the logic and physical abstraction levels. The use of SCCGs increases the design space (number of different primitive cells) when compared to the state-of-the-art cell based approaches. Therefore, a new design flow is defined, which replaces cell libraries by virtual components, creating in this way a virtual library. We present the procedure to create such virtual library in the Synopsys environment, and to integrate logic synthesis tools in automatic layout synthesis.