Résumé
Side channels attacks (SCA) are very effective and low cost methods to extract secret information from. supposedly secure cryptosystems. Differential Power Analysis (DPA) and Differential Electromagnetic, Analysis (DEMA) are among the most cited attack types. The traditional synchronous design flow used to create such systems favors the leakage of information that enables attackers to draw correlations between data processes and circuit power consumption or electromagnetic radiations. By using well known analysis techniques these correlations may allow that an attacker retrieve secret cryptographic keys. In recent years, several countermeasures against SCA have been. proposed. Globally Asynchronous Locally Synchronous (GALS) and fully asynchronous design methods appear as alternatives to design tamper resistant cryptosystems. However, according to previous works they use to achieve this with significant area, throughput, latency and power penalties. This paper proposes a new GALS pipeline architecture for the Data Encryption Standard (DES) that explores the trade-off between circuit area and robustness. Robustness is enhanced by replicating the DES hardware structure in asynchronously communicating module instances, coupled with self-varying operating frequencies. Designs prototyped on FPGAs using the proposed technique and submitted to DEMA attacks presented promising robustness against attacks and throughput superior to previously reported results.