Abstract
In this paper, we present a study on the effects of resistive-bridging defects in the SRAM core-cell. In particular, the position of the resistive-bridges has been chosen taking in account an actual industrial core-cell layout. We have performed an extensive number of simulations, varying the resistance value of the defects, supply voltage, frequency and temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array. Static and dynamic faults, single-cell and double-cell faults have been found.