Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme

Marie-Lise Flottes; Julien Pouget; Bruno Rouzeyre

doi:10.1007/978-0-387-35597-9_34

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Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme

Book chapter

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Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme

Marie-Lise Flottes, Julien Pouget and Bruno Rouzeyre

SOC Design Methodologies, Vol.90, pp.401-412

IFIP — The International Federation for Information Processing

2002

DOI: https://doi.org/10.1007/978-0-387-35597-9_34

Abstract

System-on-Chip

test scheduling

This paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation.

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Title: Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme
Creators - without role: Marie-Lise Flottes - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Julien Pouget - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Bruno Rouzeyre - Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Publication Details: SOC Design Methodologies, Vol.90, pp.401-412
Series: IFIP — The International Federation for Information Processing
Identifiers: 9944067009311
Academic Unit: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Language: English
Resource Type: Book chapter
Local Fields: lirmm-00268504