Interconnect Capacitance Modelling in a VDSM CMOS Technology

David Bernard; Christian Landrault; Pascal Nouet

doi:10.1007/978-0-387-35597-9_12

Back

Interconnect Capacitance Modelling in a VDSM CMOS Technology

Book chapter

Open access

Interconnect Capacitance Modelling in a VDSM CMOS Technology

David Bernard, Christian Landrault and Pascal Nouet

SOC Design Methodologies, Vol.90, pp.133-144

IFIP — The International Federation for Information Processing

2002

DOI: https://doi.org/10.1007/978-0-387-35597-9_12

Abstract

Interconnects

Capacitance

layout extraction

closed-form models

This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.

Files and links (2)

url

Find in HALView

url

https://doi.org/10.1007/978-0-387-35597-9_12View

Published (Version of record) Open

Metrics

1 Record Views

Details

Title: Interconnect Capacitance Modelling in a VDSM CMOS Technology
Creators - without role: David Bernard - Atmel
Christian Landrault - Université de Montpellier
Pascal Nouet - Université de Montpellier
Publication Details: SOC Design Methodologies, Vol.90, pp.133-144
Series: IFIP — The International Federation for Information Processing
Identifiers: 9944167009311
Academic Unit: Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
Language: English
Resource Type: Book chapter
Local Fields: lirmm-00268482