Abstract
Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out.
- Title
- Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks
- Creators - without role
- Hanitriniaina Razafindraibe - Université de Montpellier, Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMMMichel Robert - Conception et Test de Systèmes MICroélectroniquesPhilippe Maurine - Conception et Test de Systèmes MICroélectroniques
- Contributors - without role
- Nadine AzémardPhilippe MaurineJohan Vounckx
- Publication Details
- Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Vol.4148/2006, pp.634-644
- Series
- Lecture Notes in Computer Science
- Identifiers
- 9946947109311
- Academic Unit
- Laboratoire d'Informatique de Robotique et de Microélectronique de Mtp - LIRMM
- Language
- English
- Resource Type
- Book chapter
- Local Fields
- lirmm-00109844